1. Field
The present disclosure is directed to equipment for testing microcircuits.
2. Description of the Related Art
As microcircuits continually evolve to be smaller and more complex, the test equipment that tests the microcircuits also evolves. There is an ongoing effort to improve microcircuit test equipment, with improvements leading to an increase in reliability, an increase in throughput, and/or a decrease in expense.
Mounting a defective microcircuit on a circuit board is relatively costly. Installation usually involves soldering the microcircuit onto the circuit board. Once mounted on a circuit board, removing a microcircuit is problematic because the very act of melting the solder for a second time ruins the circuit board. Thus, if the microcircuit is defective, the circuit board itself is probably ruined as well, meaning that the entire value added to the circuit board at that point is lost. For all these reasons, a microcircuit is usually tested before installation on a circuit board.
Each microcircuit must be tested in a way that identifies all defective devices, but yet does not improperly identify good devices as defective. Either kind of error, if frequent, adds substantial overall cost to the circuit board manufacturing process, and can add retest costs for devices improperly identified as defective devices.
Microcircuit test equipment itself is quite complex. First of all, the test equipment must make accurate and low resistance temporary and non-destructive electrical contact with each of the closely spaced microcircuit contacts. Because of the small size of microcircuit contacts and the spacings between them, even small errors in making the contact will result in incorrect connections. Connections to the microcircuit that are misaligned or otherwise incorrect will cause the test equipment to identify the device under test (DUT) as defective, even though the reason for the failure is the defective electrical connection between the test equipment and the DUT rather than defects in the DUT itself.
A further problem in microcircuit test equipment arises in automated testing. Testing equipment may test 100 devices a minute, or even more. The sheer number of tests cause wear on the tester contacts making electrical connections to the microcircuit terminals during testing. This wear dislodges conductive debris from both the tester contacts and the DUT terminals that contaminates the testing equipment and the DUTs themselves.
The debris eventually results in poor electrical connections during testing and false indications that the DUT is defective. The debris adhering to the microcircuits may result in faulty assembly unless the debris is removed from the microcircuits. Removing debris adds cost and introduces another source of defects in the microcircuits themselves.
Other considerations exist as well. Inexpensive tester contacts that perform well are advantageous. Minimizing the time required to replace them is also desirable, since test equipment is expensive. If the test equipment is off line for extended periods of normal maintenance, the cost of testing an individual microcircuit increases.
Test equipment in current use has an array of test contacts that mimic the pattern of the microcircuit terminal array. The array of test contacts is supported in a structure that precisely maintains the alignment of the contacts relative to each other. An alignment plate or board aligns the microcircuit itself with the test contacts. Many times the alignment plate is separate from the housing that houses the contacts because it tends to wear and need replacing more often. The test housing and the alignment plate are mounted on a load board having conductive pads that make electrical connection to the test contacts. The load board pads are connected to circuit paths that carry the signals and power between the test equipment electronics and the test contacts.
For the electrical tests, it is desired to form a temporary electrical connection between each terminal on the device under test and a corresponding electrical pad on a load board. In general, it is impractical to solder and remove each electrical terminal on the microcircuit being contacted by a corresponding electrical probe on the testbed. Instead of soldering and removing each terminal, the tester may employ a series of electrically conductive contacts arranged in a pattern that corresponds to both the terminals on the device under test and the electrical pads on the load board. When the device under test is forced into contact with the tester, the contacts complete the circuits between respective device under test contacts and corresponding load board pads. After testing, when the device under test is released, the terminals separate from the contacts and the circuits are broken.
The present application is directed to improvements to these contacts.
There is a type of testing known as “Kelvin” testing, which accurately measures the resistance between two terminals on the device under test. Basically, Kelvin testing involves forcing a current to flow between the two terminals, measuring the voltage difference between the two terminals, and using Ohm's Law to derive the resistance between the terminals, given as the voltage divided by the current. Each terminal on the device under test is electrically connected to two contacts and their associated pads on the load board. One of the two pads supplies a known amount of current. The other pad, known as the “sense” connection, is a high-impedance connection that acts as a voltmeter, which does not draw any significant amount of current. In other words, each terminal on the device under test that is to undergo Kelvin testing is simultaneously electrically connected to two pads on the load board—one pad supplying a known amount of current and the other pad measuring a voltage and drawing an insignificant amount of current while doing so. The terminals are Kelvin tested two at a time, so that a single resistance measurement uses two terminals on the load board and four contact pads.
In this application, the contacts that form the temporary electrical connections between the device under test and the load board may be used in several manners. In a “standard” test, each contact connects a particular terminal on the device under test to a particular pad on the load board, with the terminals and pads being in a one-to-one relationship. For these standard tests, each terminal corresponds to exactly one pad, and each pad corresponds to exactly one terminal. In a “Kelvin” test, there are two contacts contacting each terminal on the device under test, as described above. For these Kelvin tests, each terminal on the device under test corresponds to two pads on the load board, and each pad on the load board corresponds to exactly one terminal on the device under test. Although the testing scheme may vary, the mechanical structure and use of the contacts is essentially the same, regardless of the testing scheme.
There are many aspects of the testbeds that may be incorporated from older or existing testbeds. For instance, much of the mechanical infrastructure and electrical circuitry may be used from existing test systems, and may be compatible with the electrically conductive contacts disclosed herein. Such existing systems are listed and summarized below.
An exemplary microcircuit tester is disclosed in United States Patent Application Publication Number US 2007/0202714 A1, titled “Test contact system for testing integrated circuits with packages having an array of signal and power contacts”, invented by Jeffrey C. Sherry, published on Aug. 30, 2007 and incorporated by reference herein in its entirety.
For the tester of '714, a series of microcircuits is tested sequentially, with each microcircuit, or “device under test”, being attached to a testbed, tested electrically, and then removed from the testbed. The mechanical and electrical aspects of such a testbed are generally automated, so that the throughput of the testbed may be kept as high as possible.
In '714, a test contact element for making temporary electrical contact with a microcircuit terminal comprises at least one resilient finger projecting from an insulating contact membrane as a cantilevered beam. The finger has on a contact side thereof, a conducting contact pad for contacting the microcircuit terminal. Preferably the test contact element has a plurality of fingers, which may advantageously have a pie-shaped arrangement. In such an arrangement, each finger is defined at least in part by two radially oriented slots in the membrane that mechanically separate each finger from every other finger of the plurality of fingers forming the test contact element.
In '714, a plurality of the test contact elements can form a test contact element array comprising the test contact elements arranged in a predetermined pattern. A plurality of connection vias are arranged in substantially the predetermined pattern of the test contacts elements, with each of said connection vias is aligned with one of the test contact elements. Preferably, an interface membrane supports the plurality of connection vias in the predetermined pattern. Numerous vias can be embedded into the pie pieces away from the device contact area to increase life. Slots separating fingers could be plated to create an I-beam, thereby preventing fingers from deforming, and also increasing life.
The connection vias of '714 may have a cup shape with an open end, with the open end of the cup-shaped via contacting the aligned test contact element. Debris resulting from loading and unloading DUTs from the test equipment can fall through the test contact elements where the cup-shaped vias impound the debris.
The contact and interface membranes of '714 may be used as part of a test receptacle including a load board. The load board has a plurality of connection pads in substantially the predetermined pattern of the test contacts elements. The load board supports the interface membrane with each of the connection pads on the load board substantially aligned with one of the connection vias and in electrical contact therewith.
In '714, the device uses a very thin conductive plate with retention properties that adheres to a very thin non-conductive insulator. The metal portion of the device provides multiple contact points or paths between the contacting I/O and the load board. This can be done either with a plated via hole housing or with plated through hole vias, or bumped surfaces, possibly in combination with springs, that has the first surface making contact with the second surface, i.e., the device I/O. The device I/O may be physically close to the load board, thus improving electrical performance.
One particular type of microcircuit often tested before installation has a package or housing having what is commonly referred to as a ball grid array (BGA) terminal arrangement. A typical BGA package may have the form of a flat rectangular block, with typical sizes ranging from 5 mm to 40 mm on a side and 1 mm thick.
A typical microcircuit has a housing enclosing the actual circuitry. Signal and power (S&P) terminals are on one of the two larger, flat surfaces, of the housing. Typically, terminals occupy most of the area between the surface edges and any spacer or spacers. Note that in some cases, a spacer may be an encapsulated chip or a ground pad.
Each of the terminals may include a small, approximately spherical solder ball that firmly adheres to a lead from the internal circuitry penetrating surface, hence the term “ball grid array.” Each terminal and spacer project a small distance away from the surface, with the terminals projecting farther from the surface than the spacers. During assembly, all terminals are simultaneously melted, and adhere to suitably located conductors previously formed on the circuit board.
The terminals themselves may be quite close to each other. Some have centerline spacings of as little as 0.25 mm, and even relatively widely spaced terminals may still be around 1.5 mm apart. Spacing between adjacent terminals is often referred to as “pitch.”
In addition to the factors mentioned above, BGA microcircuit testing involves additional factors.
First, in making the temporary contact with the ball terminals, the tester should not damage the S&P terminal surfaces that contact the circuit board, since such damage may affect the reliability of the solder joint for that terminal.
Second, the testing process is more accurate if the length of the conductors carrying the signals is kept short. An ideal test contact arrangement has short signal paths.
Third, solders commonly in use today for device terminals are mainly tin for environmental purposes. Tin-based solder alloys are likely to develop an oxide film on the outer surface that conducts poorly. Older solder alloys include substantial amounts of lead, which do not form oxide films. The test contacts must be able to penetrate the oxide film present.
BGA test contacts currently known and used in the art employ spring contacts made up of multiple pieces including a spring, a body and top and bottom plungers.
United States Patent Application Publication No. US 2003/0192181 A1, titled “Method of making an electronic contact” and published on Oct. 16, 2003, shows microelectronic contacts, such as flexible, tab-like, cantilever contacts, which are provided with asperities disposed in a regular pattern. Each asperity has a sharp feature at its tip remote from the surface of the contact. As mating microelectronic elements are engaged with the contacts, a wiping action causes the sharp features of the asperities to scrape the mating element, so as to provide effective electrical interconnection and, optionally, effective metallurgical bonding between the contact and the mating element upon activation of a bonding material.
According to United States Patent Application Publication No. US 2004/0201390 A1, titled “Test interconnect for bumped semiconductor components and method of fabrication” and published on Oct. 14, 2004, an interconnect for testing semiconductor components includes a substrate, and contacts on the substrate for making temporary electrical connections with bumped contacts on the components. Each contact includes a recess and a pattern of leads cantilevered over the recess configured to electrically engage a bumped contact. The leads are adapted to move in a z-direction within the recess to accommodate variations in the height and planarity of the bumped contacts. In addition, the leads can include projections for penetrating the bumped contacts, a non-bonding outer layer for preventing bonding to the bumped contacts, and a curved shape which matches a topography of the bumped contacts. The leads can be formed by forming a patterned metal layer on the substrate, by attaching a polymer substrate with the leads thereon to the substrate, or by etching the substrate to form conductive beams.
According to U.S. Pat. No. 6,246,249 B1, titled “Semiconductor inspection apparatus and inspection method using the apparatus” and issued on Jun. 12, 2001 to Fukasawa, et al., a semiconductor inspection apparatus performs a test on a to-be-inspected device which has a spherical connection terminal. This apparatus includes a conductor layer formed on a supporting film. The conductor layer has a connection portion. The spherical connection terminal is connected to the connection portion. At least a shape of the connection portion is changeable. The apparatus further includes a shock absorbing member, made of an elastically deformable and insulating material, for at least supporting the connection portion. A test contact element of the invention for making temporary electrical contact with a microcircuit terminal comprises at least one resilient finger projecting from an insulating contact membrane as a cantilevered beam. The finger has on a contact side thereof, a conducting contact pad for contacting the microcircuit terminal.
In U.S. Pat. No. 5,812,378, titled “Microelectronic connector for engaging bump leads” and issued on Sep. 22, 1998 to Fjelstad, et al., a connector for microelectronic includes a sheet-like body having a plurality of holes, desirably arranged in a regular grid pattern. Each hole is provided with a resilient laminar contact such as a ring of a sheet metal having a plurality of projections extending inwardly over the hole of a first major surface of the body. Terminals on a second surface of the connector body are electrically connected to the contacts. The connector can be attached to a substrate such a multi-layer circuit panel so that the terminals on the connector are electrically connected to the leads within the substrate. Microelectronic elements having bump leads thereon may be engaged with the connector and hence connected to the substrate, by advancing the bump leads into the holes of the connector to engage the bump leads with the contacts. The assembly can be tested, and if found acceptable, the bump leads can be permanently bonded to the contacts.
According to United States Patent Application Publication No. US 2001/0011907 A1, titled “Test interconnect for bumped semiconductor components and method of fabrication” and published on Aug. 9, 2001, an interconnect for testing semiconductor components includes a substrate, and contacts on the substrate for making temporary electrical connections with bumped contacts on the components. Each contact includes a recess and a support member over the recess configured to electrically engage a bumped contact. The support member is suspended over the recess on spiral leads formed on a surface of the substrate. The spiral leads allow the support member to move in a z-direction within the recess to accommodate variations in the height and planarity of the bumped contacts. In addition, the spiral leads twist the support member relative to the bumped contact to facilitate penetration of oxide layers thereon. The spiral leads can be formed by attaching a polymer substrate with the leads thereon to the substrate, or by forming a patterned metal layer on the substrate. In an alternate embodiment contact, the support member is suspended over the surface of the substrate on raised spring segment leads.
Consider an electrical chip that is manufactured to be incorporated into a larger system. When in use, the chip electrically connects the device to the larger system by a series of contacts or terminals. For instance, the contacts on the electrical chip may plug into corresponding sockets in a computer, so that the computer circuitry may electrically connect with the chip circuitry in a predetermined manner. An example of such a chip may be a memory card or processor for a computer, each of which may be insertable into a particular slot or socket that makes one or more electrical connections with the chip.
It is highly desirable to test these chips before they are shipped, or before they are installed into other systems. Such component-level testing may help diagnose problems in the manufacturing process, and may help improve system-level yields for systems that incorporate the chips. Therefore, sophisticated test systems have been developed to ensure that the circuitry in the chip performs as designed. The chip is attached to the tester, as a “device under test”, is tested, and is then detached from the tester. In general, it is desirable to perform the attachment, testing, and detachment as rapidly as possible, so that the throughput of the tester may be as high as possible.
The test systems access the chip circuitry through the same contacts or terminals that will later be used to connect the chip in its final application. As a result, there are some general requirements for the test system that perform the testing. In general, the tester should establish electrical contact with the various contacts or terminals so that the contacts are not damaged, and so that a reliable electrical connection is made with each contact.
Most testers of this type use mechanical contacts between the chip I/O contacts and the tester contacts, rather than soldering and de-soldering or some other attachment method. When the chip is attached to the tester, each contact on the chip is brought into mechanical and electrical contact with a corresponding pad on the tester. After testing, the chip is removed from the tester, and the mechanical and electrical contacts are broken.
In general, it is highly desirable that the chip and the tester both undergo as little damage as possible during the attachment, testing, and detachment procedures. Pad layouts on the tester may be designed to reduce or minimize wear or damage to the chip contacts. For instance, it is not desirable to scrape the device I/O (leads, contacts, pads or balls), bend or deflect the I/O, or perform any operation that might permanently change or damage the I/O in any way. Typically, the testers are designed to leave the chips in a final state that resembles the initial state as closely as possible. In addition, it is also desirable to avoid or reduce any permanent damage to the tester or tester pads, so that tester parts may last longer before replacement.
There is currently a great deal of effort spent by tester manufacturers on the pad layouts. For instance, the pads may include a spring-load mechanism that receives the chip contacts with a prescribed resisting force. In some applications, the pads may have an optional hard stop at the extreme end of the spring-load force range of travel. The goal of the pad layout is to establish a reliable electrical connection with the corresponding chip contacts, which may be as close as possible to a “closed” circuit when the chip is attached, and may be as close as possible to an “open” circuit when the chip is detached.
Because it is desirable to test these chips as quickly as possible, or simulate their actual use in a larger system, it may be necessary to drive and/or receive electrical signals from the contacts at very high frequencies. The test frequencies of current-day testers may be up to 40 GHz or more, and the test frequencies are likely to increase with future generation testers.
For low-frequency testing, such as that done close to DC (0 Hz), the electrical performance may be handled rather simplistically: one would want an infinitely high resistance when the chip is detached, and an infinitesimally small resistance when the chip is attached.
At higher frequencies, other electrical properties come into play, beyond just resistance. Impedance (or, basically, resistance as a function of frequency) becomes a more proper measure of electrical performance at these higher frequencies. Impedance may include phase effects as well as amplitude effects, and can also incorporate and mathematically describe the effects of resistance, capacitance and inductance in the electrical path. In general, it is desirable that the contact resistance in the electrical path formed between the chip I/O and the corresponding pad on the load card be sufficiently low, which maintains a target impedance of 50 ohms, so that the tester itself does not significantly distort the electrical performance of the chip under test. Note that most test equipment is designed to have 50 ohm input and output impedances.
For modern-day chips that have many, many closely spaced I/O, it becomes helpful to simulate the electrical and mechanical performance at the device I/O interface. Finite-element modeling in two- or three dimensions has become a tool of choice for many designers. In some applications, once a basic geometry style has been chosen for the tester pad configuration, the electrical performance of the pad configuration is simulated, and then the specific sizes and shapes may be iteratively tweaked until a desired electrical performance is achieved. For these applications, the mechanical performance may be determined almost as an afterthought, once the simulated electrical performance has reached a particular threshold.